The present invention relates to methods of fabricating semiconductor devices which facilitate reducing parasitic capacitance and improving oxidation protection.
As devices shrink and new metals such as tungsten (W) are required for semiconductors, it becomes much more difficult to control and tolerate gate metal oxidation. Formation of metal oxide during selective oxidation of the gate metal results in gate sidewalls having ridges or bumps at the location of the gate metal due to extrusion of the metal oxide forming there. When a spacer is then deposited, it tends to be thinner on the gate sidewalls where the metal oxide extrudes. A thin spacer may cause gate metal oxidation during following oxide deposition and steam anneal and may result in gate metal opens or shorts.
A schematic of the gate stack of a typical transistor 100 is shown in FIG. 1, where the stack composes gate cap nitride 105, conductive metal 104 (such as W or WSix), and polysilicon 103. A gate oxide 102 separates the gate stack from the Si substrate 101. The shape of the stack is defined by lithographic masking and reactive ion etch (“RIE”) steps. The sidewall 109 of the gate stack is normally smooth after the stack is formed but prior to selective oxidation.
Turning to FIG. 2, a selective oxidation anneal is typically performed after the stack is formed to improve gate oxide reliability. The metal 204 surface is also oxidized during the oxidation anneal and the metal oxide 206 extrudes towards the sides of the stack, in part due to the volume expansion.
As depicted in FIG. 3, after selective oxidation and ion implants, a gate spacer 307 (commonly,Si3N4) is deposited on the stack. A blanket RIE is performed to remove the Si3N4 from the gate oxide surface. The spacer 307 is deposited in a thinner layer on the gate metal 304 due to the metal oxide 306 extrusion. This thinner spacer layer results in an undesirable increase in metal oxidation during the following oxide deposition and steam anneal, and also possibly causes unwanted gate metal-to-gate metal or wordline-to-bitline shorts.
A need exists for a process of semiconductor fabrication that prevents thinning of the gate spacer on the gate metal due to metal oxide extrusion.